1. Field of the Invention
This invention relates to the reduction of power consumption in high frequency data processing systems, and more particularly to the reduction of peak power demands by injecting delays when a predetermined number of data transfer paths indicate long periods of high-speed, high-volume switching activity.
2. Description of the Prior Art
Data processing systems, especially multi-processing systems, often allow simultaneous data transfers to be made to multiple components. These data transfers can be to cache memories, main storage memories, or even to peripheral devices. Multiple data transfers, coupled with high data switching frequencies, can result in high system power consumption. The power consumed by the system is directly related to the switching frequency. The switching frequency is affected by the system clock frequency, and by the binary data values to be clocked relative to the previous value. High system clock frequency is desirable for the obvious reason of increasing the operation speed of the data processing system. The power consumption due to the system clock frequency is predictable, but the power consumption due to toggling of the binary data values depends on the rate at which the binary data values actually change logic states. For instance, a single data value switching from time t=0 to a later time t=T having the following data pattern ##STR1## will consume more power than where the data pattern is ##STR2## due to the higher rate of logic state switching. Where multiple data transfers are simultaneously occurring, and each data transfer consists of multiple bytes, the power consumption can be great.
Under normal circumstances, however, it is unlikely that all data transfer interfaces will be simultaneously active, and that each data transfer will have data patterns consisting of continuously alternating logic states. Therefore, under normal operating conditions, the power consumption can be estimated by an "average worst case" analysis. However, for system test purposes, Diagnostic Verification Routines (DVRs) are written to continuously alternate the logic states of the data, in order to fully test the data transfer circuitry and receiving circuitry. Furthermore, it is theoretically possible that such data patterns could occur during real-time operation of the system.
In order to provide sufficient power capability, the power supplies must provide voltage and current adequate to meet this absolute worst-case situation. This results in larger, more expensive power supplies than those that would be necessary for the average worst-case situation. Since the absolute worst-case situation would occur only in exceptional circumstances, it would be a waste of resources to implement large, expensive power supplies to handle this rare event. The present invention solves this problem, and allows for utilization of smaller, less expensive power supplies which are capable of providing adequate power in the "average worst-case" situation.
The present invention uses inexpensive circuitry to determine when a predetermined threshold of data transfer activity is reached. When this threshold is reached, temporary delays are injected into the data transfer handshake loop to temporarily reduce the data transfer rates, which in turn will reduce the power consumption during this time period. Expensive, large-capacity power supplies are therefore not necessary, and the added cost of the additional circuitry is trivial compared to the cost of the larger power supplies. Furthermore, the size of the power supplies is typically proportional to the amount of power capability, and therefore valuable space is saved. The circuitry comprising the invention requires little real estate, and can actually be implemented in an existing gate array which would result in a 0% increase in real estate use. The reduction in power consumption and the temporary reduction in data transfer rates can also ease cooling requirements, and only "average" worst-case cooling capabilities would need to be implemented. The savings of space and cost of power and cooling requirements far outweighs the slight reduction in data transfer rates, particularly in light of the fact that this reduction in data transfer rates will very seldom need to be actuated.
Designs have been constructed to deal with the problem of peak power consumption. One such design is described in U.S. Pat. No. 5,201,071 by Webb, issued on Apr. 6, 1993. The Webb reference appears to disclose a method of reducing peak voltages of an RF transmitter by shifting the tones of a second sideband from those in a first sideband. Webb discloses a delay circuit that may be used to create such a phase shift (column 4, lines 37-49). However, the delay method used to generate a phase shift in Webb is not used in the present invention. In the present invention, the delay circuitry delays the acknowledge signal in a handshaking arrangement to temporarily reduce the rate of data transfers. Furthermore, the delay in the Webb reference is always activated, where the delay circuitry in the present invention is only activated when necessary.
The "Dynamic Power Regulator For Controlling Memory Power Consumption" thus provides a way to reduce system costs and system space requirements, while still resolving absolute worst-case scenarios. The additional cost and space requirements of the present invention is little to none, and the time delay penalty for injecting delays will be virtually nonexistent (and most likely completely nonexistent) over time.